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D-type flip-flops
Dual D-type pos.-edge-triggered flip-flops with preset and clear
Data sheet
- document-pdfAcrobat Dual D-Type Positive-Edge -Triggered Flip-Flops With Preset And Clear datasheet
SN74LS74A
Product details
- Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
- Dependable Texas Instruments Quality and Reliability
- Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
- Dependable Texas Instruments Quality and Reliability
These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.
The SN54' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74' family is characterized for operation from 0°C to 70°C.
These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.
The SN54' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74' family is characterized for operation from 0°C to 70°C.
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Technical documentation
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View all 11Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | Dual D-Type Positive-Edge -Triggered Flip-Flops With Preset And Clear datasheet | 01 Mar 1988 | |
Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 15 Dec 2022 | |
Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
Application note | Designing with the SN54/74LS123 (Rev. A) | 01 Mar 1997 | ||
Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 Oct 1996 | ||
Application note | Live Insertion | 01 Oct 1996 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
Evaluation board
14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages
The 14-24-LOGIC-EVM evaluation module(EVM)is designed to support any logic device that is in a 14-pin to 24-pinD, DW, DB, NS, PW, DYYor DGV package,
User guide: PDF | HTML
Not available on TI.com
Package | Pins | CAD symbols, footprints & 3D models |
---|---|---|
PDIP (N) | 14 | Ultra Librarian |
SOIC (D) | 14 | Ultra Librarian |
SOP (NS) | 14 | Ultra Librarian |
SSOP (DB) | 14 | Ultra Librarian |
TI's Standard Terms and Conditions for Evaluation Items apply.
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